Sundance-spas ST201 Instrukcja Użytkownika

ST201Fast Ethernet MACSee Sundance Technology’s website at www.sundanceti.com for the latest information.Sundance TechnologyPublication: 2 Rev: ADate:

10Sundance Technology ST201 PRELIMINARY draft 2ACRONYMS AND GLOSSARYLAN Local Area NetworkMAC Media Access Control Layer, or adevice implementing the

100Sundance Technology ST201 PRELIMINARY draft 2OCTETSRECEIVEDOKClass...I/O Registers, StatisticsBase Address ...IoBaseAddress reg

101Sundance Technology ST201 PRELIMINARY draft 2OCTETSTRANSMITTEDOKClass...I/O Registers, StatisticsBase Address ...IoBaseAddress

102Sundance Technology ST201 PRELIMINARY draft 2SINGLECOLLISIONFRAMESClass...I/O Registers, StatisticsBase Address ...IoBaseAddres

103Sundance Technology ST201 PRELIMINARY draft 2PCI CONFIGURATION REGISTERSPCI based systems use a slot-specific block of configuration registers to p

104Sundance Technology ST201 PRELIMINARY draft 2byte 3 byte 2 byte 1 byte 0 OffsetFIGURE 12: ST201 PCI Register LayoutReserved PowerMgmtCtrl 0x54Reser

105Sundance Technology ST201 PRELIMINARY draft 2CACHELINESIZEClass...PCI Configuration Registers, ConfigurationBase Address ...PCI

106Sundance Technology ST201 PRELIMINARY draft 2CAPPTRClass...PCI Configuration Registers, ConfigurationBase Address ...PCI device

107Sundance Technology ST201 PRELIMINARY draft 2CLASSCODEClass...PCI Configuration Registers, ConfigurationBase Address ...PCI dev

108Sundance Technology ST201 PRELIMINARY draft 2CONFIGCOMMANDClass...PCI Configuration Registers, ConfigurationBase Address ...PCI

109Sundance Technology ST201 PRELIMINARY draft 2CONFIGSTATUSClass...PCI Configuration Registers, ConfigurationBase Address ...PCI

11Sundance Technology ST201 PRELIMINARY draft 2PCI BUS INTERFACEThe PCI Bus Interface (PBI) implements the proce-dures and algorithms needed to link t

110Sundance Technology ST201 PRELIMINARY draft 2DEVICEIDClass...PCI Configuration Registers, ConfigurationBase Address ...PCI devi

111Sundance Technology ST201 PRELIMINARY draft 2EXPROMBASEADDRESSClass...PCI Configuration Registers, ConfigurationBase Address ...

112Sundance Technology ST201 PRELIMINARY draft 2HEADERTYPEClass...PCI Configuration Registers, ConfigurationBase Address ...PCI de

113Sundance Technology ST201 PRELIMINARY draft 2INTERRUPTLINEClass...PCI Configuration Registers, ConfigurationBase Address ...PCI

114Sundance Technology ST201 PRELIMINARY draft 2INTERRUPTPINClass...PCI Configuration Registers, ConfigurationBase Address ...PCI

115Sundance Technology ST201 PRELIMINARY draft 2IOBASEADDRESSClass...PCI Configuration Registers, ConfigurationBase Address ...PCI

116Sundance Technology ST201 PRELIMINARY draft 2LATENCYTIMERClass...PCI Configuration Registers, ConfigurationBase Address ...PCI

117Sundance Technology ST201 PRELIMINARY draft 2MAXLATClass...PCI Configuration Registers, ConfigurationBase Address ...PCI device

118Sundance Technology ST201 PRELIMINARY draft 2MEMBASEADDRESSClass...PCI Configuration Registers, ConfigurationBase Address ...PC

119Sundance Technology ST201 PRELIMINARY draft 2MINGNTClass...PCI Configuration Registers, ConfigurationBase Address ...PCI device

12Sundance Technology ST201 PRELIMINARY draft 2EXPANSION ROM INTERFACEThe ST201 provides support for an optional Expan-sion ROM. The ST201 supports th

120Sundance Technology ST201 PRELIMINARY draft 2REVISIONIDClass...PCI Configuration Registers, ConfigurationBase Address ...PCI de

121Sundance Technology ST201 PRELIMINARY draft 2SUBSYSTEMIDClass...PCI Configuration Registers, ConfigurationBase Address ...PCI d

122Sundance Technology ST201 PRELIMINARY draft 2SUBSYSTEMVENDORIDClass...PCI Configuration Registers, ConfigurationBase Address ...

123Sundance Technology ST201 PRELIMINARY draft 2VENDORIDClass...PCI Configuration Registers, ConfigurationBase Address ...PCI devi

124Sundance Technology ST201 PRELIMINARY draft 2CAPIDClass...PCI Configuration Registers, Power ManagementBase Address ...PCI devi

125Sundance Technology ST201 PRELIMINARY draft 2NEXTITEMPTRClass...PCI Configuration Registers, Power ManagementBase Address ...PC

126Sundance Technology ST201 PRELIMINARY draft 2POWERMGMTCAPClass...PCI Configuration Registers, Power ManagementBase Address ...P

127Sundance Technology ST201 PRELIMINARY draft 2POWERMGMTCTRLClass...PCI Configuration Registers, Power ManagementBase Address ...

128Sundance Technology ST201 PRELIMINARY draft 2EEPROM DATA FORMATFigure 13 summarizes the layout of the EEPROM.byte 0 OffsetFIGURE 13: EEPROM Data La

129Sundance Technology ST201 PRELIMINARY draft 2CONFIGPARMClass...EEPROM Data FormatBase Address ...0x00, address written to Eepro

13Sundance Technology ST201 PRELIMINARY draft 2dress register. Setting the ReceiveBroadcast andReceiveMulticast bits in the ReceiveMode registerwill a

130Sundance Technology ST201 PRELIMINARY draft 2STATIONADDRESSClass...EEPROM Data FormatBase Address ...0x00, address written to E

131Sundance Technology ST201 PRELIMINARY draft 2ASICCTRLClass...EEPROM Data FormatBase Address ...0x00, address written to EepromC

132Sundance Technology ST201 PRELIMINARY draft 214..8 Reserved Reserved for future use. Should be set to 0.15 ResetPolarity Setting this read/write bi

133Sundance Technology ST201 PRELIMINARY draft 2SUBSYSTEMVENDORIDClass...EEPROM Data FormatBase Address ...0x00, address written t

134Sundance Technology ST201 PRELIMINARY draft 2SUBSYSTEMIDClass...EEPROM Data FormatBase Address ...0x00, address written toEepro

135Sundance Technology ST201 PRELIMINARY draft 2ABSOLUTE MAXIMUM RATINGSStorage Temperature ...-65ºC to +150ºCAmbient Temperature...

136Sundance Technology ST201 PRELIMINARY draft 2DC CHARACTERISTICSDC characteristics are defined over commercial operating ranges unless specified oth

137Sundance Technology ST201 PRELIMINARY draft 2PIN TYPE OD6 (OPEN DRAIN OUTPUT BUFFER)VOLOutput low voltage IOL = 6mA 0.4 VIOZOutput leakage current

138Sundance Technology ST201 PRELIMINARY draft 2MISC INTERFACEITU/OT4 GPIO0, GPIO1OT4 RSTOUTOD8 LEDPWRN, LEDLNKN, LEDDPLXN, LEDSPDNOC4 CLK25OSCI X25I

139Sundance Technology ST201 PRELIMINARY draft 2SWITCHING CHARACTERISTICSPARAMETER SYMBOLPARAMETER DESCRIPTIONTEST CONDITIONS MIN MAX UNITPCI INTERFAC

14Sundance Technology ST201 PRELIMINARY draft 2TXDMA AND FRAME TRANSMISSIONThe TxDMA block transfers frame data from a hostsystem to the ST201 based o

140Sundance Technology ST201 PRELIMINARY draft 2TwhEWEN write cycle high 100 - -TwlEWEN write cycle low 90 - -EEPROM INTERFACETskcEESK cycle 1us - -Ts

141Sundance Technology ST201 PRELIMINARY draft 2MII INTERFACE - MANAGEMENTTccMDC cycle 400 - -TchMDC high 160 - -TclMDC low 160 - -TsuMDIO setup wrt M

142Sundance Technology ST201 PRELIMINARY draft 2tabcST201RSTNPCICLKGNTNREQNBUSSEDtrctcltcctchtrvtrvptrvptroztsutsup2trzotsup1thdtrstoffSIGNALSANY SIGN

143Sundance Technology ST201 PRELIMINARY draft 2EECSEESKEEDIEEDOD0D15A7 A0tcstskltcsktskhtpdtdostdohtcshST201FIGURE 16: EEPROM Switching Characteristi

144Sundance Technology ST201 PRELIMINARY draft 2ST201trvtrhtrhtcltcctchtsuthdtcltcctchtsuthdtsuthdtrvtrvthdtcltcctchTXD[3..0]TXENTXCLKRXD[3..0]RXERRXD

Copyright Sundance Technology, Inc., 1998. The information contained in this data sheet is subject to change without notice. Sun-dance Technology assu

15Sundance Technology ST201 PRELIMINARY draft 2The TxDMAListPtr I/O register within the ST201contains the physical address that points to thehead o

16Sundance Technology ST201 PRELIMINARY draft 2are independent of each other in general. A specialcase is when a transmit under run occurs. In thiscas

17Sundance Technology ST201 PRELIMINARY draft 2received and transferred by RxDMA, a RxDMA-Complete interrupt will be generated for eachframe.The host

18Sundance Technology ST201 PRELIMINARY draft 2Systems using the ST201 can be programmed togenerate an interrupt based upon the number ofbytes that ha

19Sundance Technology ST201 PRELIMINARY draft 2STATISTICSThe ST201 implements 16 statistics counters ofvarious widths. Each statistic implemented com

2Sundance Technology ST201 PRELIMINARY draft 2BLOCK DIAGRAMPHYLNKNRSTNPCICLKGNTNIDSELINTANWAKEREQNAD[31..0]CBEN[3:0]PARFRAMENIRDYNTRDYNDEVSELNSTOPNPER

20Sundance Technology ST201 PRELIMINARY draft 2disable the use of MWI and MRL. MWIDisable andMRLDisable are cleared by default, enabling MWIand MRL.Th

21Sundance Technology ST201 PRELIMINARY draft 2D1, D2, or D3. When the ST201 detects a WakePacket, it signals a wake event on PMEN (if PMENassertion i

22Sundance Technology ST201 PRELIMINARY draft 2network via transmission of a special frame. Oncethe ST201 has been placed in Magic Packet modeand put

23Sundance Technology ST201 PRELIMINARY draft 23. Set MgmtClk4. Write the desired data bit to MgmtData5. Wait a minimum of 200 nsTo perform a Z cycle

24Sundance Technology ST201 PRELIMINARY draft 28. Verify EepromBusy is false.9. Issue WriteRegister command(opcode = 01 aaaa aaaa)Step 4 through 8 may

25Sundance Technology ST201 PRELIMINARY draft 2tion of the “first TFD” in the TxDMAList. Restore the TxDMANextPtr of the “first TFD”, and restart this

26Sundance Technology ST201 PRELIMINARY draft 2host system then returns to the operating sys-tem an indication of readiness to be powered down (making

27Sundance Technology ST201 PRELIMINARY draft 2REGISTERS AND DATA STRUCTURESDMA DATA STRUCTURESA TFD is used to move data, which is to be transmitted

28Sundance Technology ST201 PRELIMINARY draft 2TXDMAFRAGADDRClass...DMA Data Structures, TFDBase Address ...Start of TFDAddress Of

29Sundance Technology ST201 PRELIMINARY draft 2TXDMAFRAGLENClass...DMA Data Structures, TFDBase Address ...Start of TFDAddress Off

3Sundance Technology ST201 PRELIMINARY draft 2ORDERING INFORMATIONK CTEMPERATURE RANGEPACKAGE TYPEDEVICE NUMBER/DESCRIPTIONST201C=Commercial (0 to +70

30Sundance Technology ST201 PRELIMINARY draft 2TXDMANEXTPTRClass...DMA Data Structures, TFDBase Address ...Start of TFDAddress Off

31Sundance Technology ST201 PRELIMINARY draft 2TXFRAMECONTROLClass...DMA Data Structures, TFDBase Address ...Start of TFDAddress O

32Sundance Technology ST201 PRELIMINARY draft 2RXDMANEXTPTRClass...DMA Data Structures, RFDBase Address ...Start of RFDAddress Off

33Sundance Technology ST201 PRELIMINARY draft 2RXFRAMESTATUSClass...DMA Data Structures, RFDBase Address ...Start of RFDAddress Of

34Sundance Technology ST201 PRELIMINARY draft 222..21 Reserved Reserved for future use. Should be set to 0.23 DribbleBits Indicates that the frame had

35Sundance Technology ST201 PRELIMINARY draft 2RXDMAFRAGADDRClass...DMA Data Structures, RFDBase Address ...Start of RFDAddress Of

36Sundance Technology ST201 PRELIMINARY draft 2RXDMAFRAGLENClass...DMA Data Structures, RFDBase Address ...Start of RFDAddress Off

37Sundance Technology ST201 PRELIMINARY draft 2WAKE EVENT DATA STRUCTURESThe first Wake Event Data Structure is the Pseudo Packet. A Pseudo Packet is

38Sundance Technology ST201 PRELIMINARY draft 2PSEUDOPATTERNClass...Wake Event Data Structures, Pseudo PacketBase Address ...Start

39Sundance Technology ST201 PRELIMINARY draft 2TERMINATORClass...Wake Event Data Structures, Pseudo PacketBase Address ...Start of

4Sundance Technology ST201 PRELIMINARY draft 2PIN DIAGRAM

40Sundance Technology ST201 PRELIMINARY draft 2PSEUDOCRCClass...Wake Event Data Structures, Pseudo PacketBase Address ...Start of

41Sundance Technology ST201 PRELIMINARY draft 2MAGICSYNCSTREAMClass...Wake Event Data Structures, Magic PacketBase Address ...Star

42Sundance Technology ST201 PRELIMINARY draft 2MAGICSEQUENCEClass...Wake Event Data Structures, Magic PacketBase Address ...Start

43Sundance Technology ST201 PRELIMINARY draft 2I/O REGISTERSThe host interacts with the ST201 mainly through slave registers, which occupy 128 bytes i

44Sundance Technology ST201 PRELIMINARY draft 2McstFramesRcvdOk McstFramesXmtdOk BcstFramesRcvdOk BcstFramesXmtdOk 0x7cFramesAbortXSColls FramesWEXDef

45Sundance Technology ST201 PRELIMINARY draft 2ASICCTRLClass...I/O Registers, Control and StatusBase Address ...IoBaseAddress regi

46Sundance Technology ST201 PRELIMINARY draft 210..8 ForcedConfig These bits are used to place the ST201 into Forced Configuration mode. The bit value

47Sundance Technology ST201 PRELIMINARY draft 219 DMA When set, together with GlobalReset, RxReset, or TxReset bits, will reset RxDMA and TxDMA Logic,

48Sundance Technology ST201 PRELIMINARY draft 2DEBUGCTRLClass...I/O Registers, Control and StatusBase Address ...IoBaseAddress reg

49Sundance Technology ST201 PRELIMINARY draft 2HASHTABLEClass...I/O Registers, Control and StatusBase Address ...IoBaseAddress reg

5Sundance Technology ST201 PRELIMINARY draft 2PIN DESIGNATIONSPIN NO.PIN NAMEPIN NO.PIN NAMEPIN NO.PIN NAMEPIN NO.PIN NAME1 VCC (5V) 33 AD9 65 EA2 97

50Sundance Technology ST201 PRELIMINARY draft 2MACCTRLClass...I/O Registers, Control and StatusBase Address ...IoBaseAddress regis

51Sundance Technology ST201 PRELIMINARY draft 29 RcvFCS This bit is set by the host if it is desired for the receive frame’s FCS tobe passed to the ho

52Sundance Technology ST201 PRELIMINARY draft 2The loopback modes available to a host system when using the ST201 are shown in Table 3.External loopba

53Sundance Technology ST201 PRELIMINARY draft 2MAXFRAMESIZEClass...I/O Registers, Control and StatusBase Address ...IoBaseAddress

54Sundance Technology ST201 PRELIMINARY draft 2RECEIVEMODEClass...I/O Registers, Control and StatusBase Address ...IoBaseAddress r

55Sundance Technology ST201 PRELIMINARY draft 2STATIONADDRESSClass...I/O Registers, Control and StatusBase Address ...IoBaseAddres

56Sundance Technology ST201 PRELIMINARY draft 2TXFRAMEIDClass...I/O Registers, Control and StatusBase Address ...IoBaseAddress reg

57Sundance Technology ST201 PRELIMINARY draft 2TXSTATUSClass...I/O Registers, Control and StatusBase Address ...IoBaseAddress regi

58Sundance Technology ST201 PRELIMINARY draft 2WAKEEVENTClass...I/O Registers, Control and StatusBase Address ...IoBaseAddress reg

59Sundance Technology ST201 PRELIMINARY draft 2FIFOCTRLClass...I/O Registers, FIFO ControlBase Address ...IoBaseAddress register v

6Sundance Technology ST201 PRELIMINARY draft 2PIN DESCRIPTIONSPIN NAME PIN TYPE PIN DESCRIPTIONPCI INTERFACERSTN INPUT Reset, asserted LOW. RSTN will

60Sundance Technology ST201 PRELIMINARY draft 2RXEARLYTHRESHClass...I/O Registers, FIFO ControlBase Address ...IoBaseAddress regis

61Sundance Technology ST201 PRELIMINARY draft 2TXRELEASETHRESHClass...I/O Registers, FIFO ControlBase Address ...IoBaseAddress reg

62Sundance Technology ST201 PRELIMINARY draft 2TXSTARTTHRESHClass...I/O Registers, FIFO ControlBase Address ...IoBaseAddress regis

63Sundance Technology ST201 PRELIMINARY draft 2COUNTDOWNClass...I/O Registers, InterruptBase Address ...IoBaseAddress register val

64Sundance Technology ST201 PRELIMINARY draft 2INTENABLEClass...I/O Registers, InterruptBase Address ...IoBaseAddress register val

65Sundance Technology ST201 PRELIMINARY draft 2INTSTATUSClass...I/O Registers, InterruptBase Address ...IoBaseAddress register val

66Sundance Technology ST201 PRELIMINARY draft 29 TxDMAComplete This bit indicates that a frame TxDMA has completed, and the TFD inquestion had the TxD

67Sundance Technology ST201 PRELIMINARY draft 2INTSTATUSACKClass...I/O Registers, InterruptBase Address ...IoBaseAddress register

68Sundance Technology ST201 PRELIMINARY draft 29 TxDMAComplete This bit indicates that a frame TxDMA has completed, and the TFD inquestion had the TxD

69Sundance Technology ST201 PRELIMINARY draft 2DMACTRLClass...I/O Registers, DMABase Address ...IoBaseAddress register valueAddres

7Sundance Technology ST201 PRELIMINARY draft 2TRDYN IN/OUT Target Ready, asserted LOW. A bus target asserts TRDYN to indicate valid read data phases,

70Sundance Technology ST201 PRELIMINARY draft 215 DMAHaltBusy This read-only bit indicates that a DMA Halt operation (TxDMAHalt orRxDMAHalt) is in pro

71Sundance Technology ST201 PRELIMINARY draft 231 MasterAbort This read-only bit is set when the ST201 experiences a master abortsequence when operati

72Sundance Technology ST201 PRELIMINARY draft 2RXDMABURSTTHRESHClass...I/O Registers, DMABase Address ...IoBaseAddress register va

73Sundance Technology ST201 PRELIMINARY draft 2RXDMALISTPTRClass...I/O Registers, DMABase Address ...IoBaseAddress register valueA

74Sundance Technology ST201 PRELIMINARY draft 2RXDMASTATUSClass...I/O Registers, DMABase Address ...IoBaseAddress register valueAd

75Sundance Technology ST201 PRELIMINARY draft 220 RxOversizedFrame Indicates the frame size was equal to or greater than the value set inthe MaxFrameS

76Sundance Technology ST201 PRELIMINARY draft 2RXDMAPOLLPERIODClass...I/O Registers, DMABase Address ...IoBaseAddress register val

77Sundance Technology ST201 PRELIMINARY draft 2RXDMAURGENTTHRESHClass...I/O Registers, DMABase Address ...IoBaseAddress register v

78Sundance Technology ST201 PRELIMINARY draft 2TXDMABURSTTHRESHClass...I/O Registers, DMABase Address ...IoBaseAddress register va

79Sundance Technology ST201 PRELIMINARY draft 2TXDMALISTPTRClass...I/O Registers, DMABase Address ...IoBaseAddress register valueA

8Sundance Technology ST201 PRELIMINARY draft 2COL INPUT Collision. COL is asserted by the PHY to a signal collision condition is detected on the physi

80Sundance Technology ST201 PRELIMINARY draft 2TXDMAPOLLPERIODClass...I/O Registers, DMABase Address ...IoBaseAddress register val

81Sundance Technology ST201 PRELIMINARY draft 2TXDMAURGENTTHRESHClass...I/O Registers, DMABase Address ...IoBaseAddress register v

82Sundance Technology ST201 PRELIMINARY draft 2EEPROMCTRLClass...I/O Registers, External Interface ControlBase Address ...IoBaseAd

83Sundance Technology ST201 PRELIMINARY draft 2EEPROMDATAClass...I/O Registers, External Interface ControlBase Address ...IoBaseAd

84Sundance Technology ST201 PRELIMINARY draft 2EXPROMADDRClass...I/O Registers, External Interface ControlBase Address ...IoBaseAd

85Sundance Technology ST201 PRELIMINARY draft 2EXPROMDATAClass...I/O Registers, External Interface ControlBase Address ...IoBaseAd

86Sundance Technology ST201 PRELIMINARY draft 2PHYCTRLClass...I/O Registers, External Interface ControlBase Address ...IoBaseAddre

87Sundance Technology ST201 PRELIMINARY draft 2STATISTICSReading a statistic register will clear it. The statistics gathering must be enabled by setti

88Sundance Technology ST201 PRELIMINARY draft 2BROADCASTFRAMESTRANSMITTEDOKClass...I/O Registers, StatisticsBase Address ...IoBase

89Sundance Technology ST201 PRELIMINARY draft 2CARRIERSENSEERRORSClass...I/O Registers, StatisticsBase Address ...IoBaseAddress re

9Sundance Technology ST201 PRELIMINARY draft 2LEDPWRN OUTPUT Power Status LED. (This pin is shared with EA9). The operation of this pin varies based o

90Sundance Technology ST201 PRELIMINARY draft 2FRAMESABORTEDDUETOXSCOLLSClass...I/O Registers, StatisticsBase Address ...IoBaseAdd

91Sundance Technology ST201 PRELIMINARY draft 2FRAMESLOSTRXERRORSClass...I/O Registers, StatisticsBase Address ...IoBaseAddress re

92Sundance Technology ST201 PRELIMINARY draft 2FRAMESRECEIVEDOKClass...I/O Registers, StatisticsBase Address ...IoBaseAddress regi

93Sundance Technology ST201 PRELIMINARY draft 2FRAMESTRANSMITTEDOKClass...I/O Registers, StatisticsBase Address ...IoBaseAddress r

94Sundance Technology ST201 PRELIMINARY draft 2FRAMESWITHDEFERREDXMISSIONClass...I/O Registers, StatisticsBase Address ...IoBaseAd

95Sundance Technology ST201 PRELIMINARY draft 2FRAMESWITHEXCESSIVEDEFERALClass...I/O Registers, StatisticsBase Address ...IoBaseAd

96Sundance Technology ST201 PRELIMINARY draft 2LATECOLLISIONSClass...I/O Registers, StatisticsBase Address ...IoBaseAddress regist

97Sundance Technology ST201 PRELIMINARY draft 2MULTICASTFRAMESRECEIVEDOKClass...I/O Registers, StatisticsBase Address ...IoBaseAdd

98Sundance Technology ST201 PRELIMINARY draft 2MULTICASTFRAMESTRANSMITTEDOKClass...I/O Registers, StatisticsBase Address ...IoBase

99Sundance Technology ST201 PRELIMINARY draft 2MULTIPLECOLLISIONFRAMESClass......I/O Registers, StatisticsBase Address ...IoBaseAddre